April 23, 2026

Intel lands Tesla as first major customer for 14A chip technology Tesla CEO Elon Musk said Tesla will use Intel's next-generation 14A process to manufacture chips for its Austin Terafab AI complex, marking Intel’s first major customer win and boosting its foundry ambitions, while Tesla expanded investment plans. Reuters

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TSMC shows smaller, faster chips without a pricey new tool from ASML TSMC unveiled next-generation chip technologies A13 and N2U, aiming for smaller, faster, cheaper chips for AI, smartphones and laptops. The company will enhance existing ASML EUV machines instead of adopting costly high-NA systems, accelerating its scaling roadmap. Reuters

Current Characterization of Various Cu RDL Designs In Wafer Level Packages (WLP) This study evaluates copper redistribution layer fusing currents in wafer-level packaging through experiments and simulations, finding that silicon thickness significantly improves heat dissipation and fusing performance. Technical Paper

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TSMC plans to open chip packaging plant in Arizona by 2029, executive says TSMC plans to open an advanced chip packaging plant in Arizona by 2029, expanding CoWoS and 3D-IC capacity. The company aims to ease AI chip bottlenecks as it brings packaging work currently done in Taiwan closer to US customers. Reuters

TSMC Unfolds Map for Process, Packaging Tech TSMC unveils chip roadmap featuring A14 1.4-nm GAA process and A13/A12 derivatives for AI and edge, alongside N2U 2-nm. It introduces photonics and advanced packaging to cut power use and latency while scaling AI data-center performance without high-NA EUV. EE Times

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Technical Papers Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications Eliminating Interfacial Delamination in High-Power Automotive Devices MORE TECHNICAL PAPERS

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Powerchip predicts substantial jump in quarterly gross margin and profits Powerchip Semiconductor Manufacturing raises chip prices amid tight supply and AI-driven demand, expects strong gross margin and profit growth this quarter. The company sees rising utilization, a return to profitability, and expanding memory, packaging, and 3D AI foundry businesses. Taipei Times

Micron pushes US Congress to curb Chinese competitors Micron Technology urges US lawmakers to pass the MATCH Act, which would tighten export controls on chipmaking equipment to China, targeting CXMT, YMTC and SMIC, while restricting foreign service access, aiming to curb China’s memory industry on national security grounds. Taipei Times

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Google unveils chips for AI training and inference in latest shot at Nvidia Google is splitting training and inference into specialized eighth-generation TPUs to challenge Nvidia in AI hardware. The chips deliver up to 2.8x training performance and 80% better inference, use SRAM-based architecture for low-latency AI agents, and see growing adoption. CNBC

AI Agent Designs a RISC-V CPU Core From Scratch In 2025, Verkor.io used its agentic AI system Design Conductor to autonomously design VerCore, a RISC-V CPU core in 12 hours, achieving performance comparable to a 2011 Intel Celeron and marking a milestone in end-to-end AI chip design. IEEE Spectrum

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Indian Researchers Develop Molecular Memristor for Neuromorphic Computing IISc Bangalore’s CeNSE researchers develop a ruthenium-based molecular memristor delivering 14-bit resolution and 4.1 TOPS/W, enabling energy-efficient neuromorphic computing. They design crossbar AI inference chips for edge applications, targeting 22 nm fabrication and startup commercialization within a year. EE Times

TSV Complexity Leads To Manufacturing Bottleneck Through-silicon vias (TSVs) connect stacked chips but shrinking dimensions increase cost, defects, and signal issues. AI-driven demand strains limited packaging capacity, while complex etch, fill and wafer thinning processes and tight tolerances challenge manufacturing yield and scalability. Semiconductor Engineering

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The Changing ASICs Landscape: the Shift Toward Chip Disaggregation AI reshapes ASIC design toward system-specific, modular, disaggregated architectures. Advanced packaging and multi-die integration optimize performance via cross-domain collaboration, but raise verification complexity, driving reusable IP, co-design, and partnerships. EE Times

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