June 19, 2026

GaN Power Devices Go Vertical Advances in gallium nitride manufacturing, engineered substrates, and doping techniques are bringing high-voltage GaN power devices closer to commercial viability. Researchers are overcoming reliability, material quality, and activation challenges, enabling compact vertical designs with kilovolt-level breakdown performance for energy and transportation applications. Semiconductor Engineering

Sponsor Automotive chips need materials that DO NOT fail We asked semiconductor specialists what defines the future of automotive packaging. Reliability, thermal management, and sustainability topped the list. Free Research Report. Henkel AG & Co.

TSMC touts glass substrate gains as Korea players race to commercialize TSMC reports validation of glass semiconductor substrates for advanced AI chip packaging, signaling progress toward commercialization. It boosts Taiwan-Japan ecosystem, heightens competition with Korean rivals, and shape next-gen packaging standards. Chosun Biz

Revolutionizing IC Packaging with High-Density RDL Technology Amkor's S-SWIFT packaging technology addresses advanced IC packaging challenges through an embedded trace RDL process, providing higher bandwidth die-to-die interconnects for AI, HPC, and data center applications with improved reliability. Technical Paper

Sponsor Real-Time Metrology Solutions Our systems uses unique Shadow Moiré vision measurement technology for flat surfaces and uses add-on Digital Fringe Projection and Digital Image Correlation technologies. Akrometrix

Making On-Chip Photonics Manufacturable Photonics is moving closer to AI processors as chipmakers pursue faster, more energy-efficient data links. Industry leaders are advancing co-packaged optics while tackling integration, heat, alignment, contamination, testing, and manufacturing challenges. Semiconductor Engineering

Intel taps industry veteran Seok-Hee Lee to lead foundry packaging push Intel appointed semiconductor veteran Seok-Hee Lee as executive vice president of its foundry division to strengthen advanced packaging and contract manufacturing. The move supports CEO Lip-Bu Tan's turnaround strategy, following partnerships with Apple, Tesla & other customers. Reuters

Sponsor See How Proven Leaders Make Operational Success Happen 4-part series addressing head-on the challenges faced by manufacturing operations in today's highly complex and hyper-competitive environment. No registration required. Intraratio

Technical Papers Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications MORE TECHNICAL PAPERS

Sponsor Plasma Etch PE-Avenger The PE-Avenger is an ultra low-cost entry level plasma cleaning system allowing more labs to utilize plasma. It's a low frequency plasma cleaner designed for surface activation and organics removal. Plasma Etch

Apple to partner with Intel Corp on chips: Trump Apple will partner with Intel to design and manufacture chips in the United States, reducing its reliance on TSMC and expanding domestic production capacity. The deal strengthens Intel's foundry business, supports US supply-chain goals & boosts investor confidence in the chipmaker. Taipei Times

Space Industry Is Standardizing on RISC-V RISC-V is gaining momentum in space computing as agencies and aerospace firms replace aging SPARC-based systems. Its open architecture cuts costs, enables customization, and provides backward-compatible migration paths for future radiation-hardened processors. EE Times

Sponsor The Leader of Advanced Packaging Thermal Solutions From 3D & CoWoS to SiP, PoP & Hybrid Bonding—we support every advanced process. Perfect reflow & curing for micro-bumping, underfill & TIM attach. Upgrade your yield. Heller Industries

Can Catalonia's Distributed Semiconductor Network Deliver? Spain's semiconductor sector is expanding through a decentralized network of research institutes and startups. As investment grows, policymakers debate whether tighter coordination or greater concentration can best strengthen chip design, photonics & advanced research. EE Times

How To Build Billions of Bumps Hybrid bonding promises billions of chip-to-chip connections at 1µm pitches, but testing every link is impractical. Experts say success hinges on uniform manufacturing, built-in test capabilities, redundancy, and defect-tolerant architectures. Semiconductor Engineering

Sponsor Auer Carries of Hermetic Packages for Seam Sealing Hermetic Packages and Covers will be sealed one at a time, with automated seam sealing using AI. The Robotic Cover Sealer (RCS) is a cleanroom seal processor. MicroCircuit Laboratories, LLC

VLSI 2026: Intel 18A Platform Momentum From Devices To Routed Designs Intel Foundry showcased major advances at VLSI 2026, highlighting Intel 18A-P and backside power technology that boost AI-era chip performance, cut power use, and improve efficiency. The company also unveiled progress in GaN, CFET, and advanced interconnect technologies. Semiconductor Engineering

Randomizing Wafers To Zero In On Process Problems Much Faster Microtronic's EAGLEview automates wafer randomization and slot-position tracking, giving fabs continuous positional analysis without added sorters, software, or test lots. The system speeds defect isolation, cuts investigation costs, and boosts manufacturing efficiency. Semiconductor Engineering

Sponsor Number 1 in bond testers Sigma is the best bond tester the market has to offer. It comes with game-changing automation capabilities for operator-free loading, testing, and analyzing. Learn more. xyztec

Automated 310mm Panel-Level Packaging to Accelerate AI Innovation: Tech Brief Panel-level packaging is gaining momentum as it boosts throughput, cuts production costs, and supports larger, more complex multi-die designs. The technology helps AI, HPC, networking & edge AI applications achieve higher performance, greater integration & faster time-to-market. Semiconductor Engineering

Sponsor AIT ORMET® TLPS for Component Attach AIT ORMET®TLPS is proven for outstanding reliability for component attaches and MLCC build-up for high temperature applications beyond 175ºC Ormet® TLPS