June 12, 2026

Mastering 3D-IC Verification Complexity As semiconductor designs adopt 2.5D and 3D-IC architectures, stacked dies, chiplets & advanced packaging create new thermal, mechanical & reliability challenges. Multiphysics verification tools help validate interfaces, power delivery & heterogeneous designs for manufacturing readiness. Semiconductor Engineering

Sponsor DIE Stacking on a Small Area Assembly process where chips are stacked on top of one another on a substrate. This vertical integration allows a compact arrangement of different circuits with different dimensions on a small area. Tresky Automation

RISC-V Targets Data Centers, Edge AI, Space RISC-V is moving beyond niche embedded uses into data centers, edge AI, and space computing. New server standards, stronger software support, and powerful chips are accelerating adoption as the open architecture challenges proprietary processors. EE Times

Eliminating Interfacial Delamination in High-Power Automotive Devices This study demonstrates that coating power devices with APTES adhesion promoter after wire bonding eliminates interfacial delamination, providing a simpler alternative to lead frame roughening technology. Technical Paper

Sponsor EZ-FLO High Precision Dispense Tips Each needle is machined from solid stainless steel as opposed to rolled tubing. The resulting smoother internal profile enhances material flow and consistency. Learn more. DL Technology

Ahead of SpaceX IPO, Elon Musk addresses ASML employees as part of push into chip manufacturing Elon Musk highlighted the importance of chip manufacturing during a virtual appearance at ASML's technology conference, as SpaceX advances its massive Terafab project in Texas. The venture aims to produce advanced chips for Tesla, SpaceX, and xAI, positioning ASML as a critical supplier. CNBC

Quantum of promise: How to build a quantum chip Quantum chipmakers are speeding development by applying proven semiconductor manufacturing methods to superconducting processors. IBM and IQM say future advances depend less on scientific breakthroughs and more on engineering, packaging & large-scale production. Data Centre Dynamics

Sponsor How to Cold Bump Pull? Learn how to perform an optimal Cold Bump Pull test on solder balls using tweezers. This guide covers test method settings and failures modes for CBP all types of bump testing. xyztec

Technical Papers Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications MORE TECHNICAL PAPERS

Sponsor Fusion and Hybrid Bonding Experts EVG's industry-leading process solutions, expertise and HI Competence Center accelerate the development and implementation of heterogeneous integration technology. EV Group

To beat chip crunch, Chinese firm inks memory deal bigger than its sales Biwin secured a US$1.86 billion, 2-year flash memory supply agreement to lock in chip capacity as AI-driven demand tightens global markets. The deal reduces supply risks, supports enterprise storage expansion & strengthens its position in the growing server and data-centre sector. South China Morning Post

Agentic AI Is Changing Data Center Architectures Agentic AI is transforming data centers as CPUs evolve from data-handling roles into orchesation hubs for reasoning, memory & security. The shift drives demand for tighter CPU-GPU integration, faster interconnects & stronger system-level verification to support autonomous AI workloads. Semiconductor Engineering

Sponsor Die-on-Tab for Compound Semiconductors This white paper explains why die-on-tab is critical for GaN and GaAs RF power devices, improving heat dissipation, reliability, and system life. Download now. StratEdge Corporation

Can AI Create Missing Models? AI is reshaping electronic design automation by reducing the cost of creating and maintaining models, enabling faster simulations and specialized workflows. However, experts caution that model accuracy, training data gaps, and domain knowledge remain critical to reliable chip design. Semiconductor Engineering

How To Start Building Edge-Native AI Edge-native AI is accelerating as inference moves from cloud data centers to devices, improving latency, privacy, and reliability. Expedera's packet-based NPU boosts utilization, reduces memory access, and delivers major gains in throughput and power efficiency. Semiconductor Engineering

Sponsor Advanced Packaging: Flexible Die Bonder Featuring a large, versatile working area, the MRSI-705 die bonder handles many input and output types, including 300mm wafers. MRSI

Building A Production-Ready Optically Connected Rack For AI Scale-Up Ayar Labs and Wiwynn are advancing co-packaged optics (CPO) to power AI clusters exceeding 1,000 accelerators. Their rack-scale, liquid-cooled infrastructure overcomes copper interconnect limits, delivering higher bandwidth, improved efficiency, and scalable hyperscale AI performance. Semiconductor Engineering

Re-Architecting Die-to-Die IO For AI Synopsys advances AI chip design with its 3DIO die-to-die interconnect IP, using hybrid bonding to increase bandwidth density while reducing power use and latency. portfolio aligns with UCIe 3D standards for scalable multi-die integration. Semiconductor Engineering

Sponsor AIT ORMET® TLPS for Proven Reliability AIT ORMET® TLPS is proven for outstanding reliability for High and Ultra High-Density Interconnection and high temperature build-up Layer Interconnection beyond 175°C Ormet® TLPS

Beyond The Demo: Deploying and Evaluating Open-Source AI Workloads CIX highlights its Armv9 platform as a practical edge AI testbed, enabling developers to deploy, observe, and optimize open-source models. Through reproducible workflows, it evaluates memory, performance, and real-world trade-offs beyond benchmarks. Semiconductor Engineering

Sponsor Rapid Package Seam Seal Changeover The Robotic Cover Sealer (RCS) enables rapid assembly changeover on < 5 minutes from a 3 x 3 mm to 50 x 70 mm package. Package tooling may be adjustable or tool less. MicroCircuit Laboratories, LLC