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Hermetic Package Seam Seal with HDHS® Technology
Brings a new level of precision and automation for hi-rel microelectronic package encapsulation, increasing seal yields to 99.99% and lowering operation costs for Aerospace, Military, Microwave, Photonics and MEMS.
MicroCircuit Laboratories, LLC
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What Year Was It?
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FDR Inaugurated
At the height of the Great Depression, Franklin Delano Roosevelt is inaugurated as the 32nd president of the United States.
See the answer below.
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Die-on-Tab for Compound Semiconductors
This white paper explains why die-on-tab is critical for GaN and GaAs RF power devices, improving heat dissipation, reliability, and system life. Download now.
StratEdge Corporation
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What Year Was It Answer
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FDR Inaugurated Answer: March 4, 1933
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A Lifespan of Reliability
Nordson Electronics Solutions makes reliable electronics an everyday reality. Selective soldering, dispensing, coating, and plasma solutions.
Nordson Electronics Solutions
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VIEWPOINT 2026: Ross Berntson, President and CEO, Indium Corporation
Innovation is at the core of our culture, and we will continue expanding our product offerings in 2026. This includes advanced packaging materials and metal thermal interface materials designed to support high-performance computing, particularly AI-driven applications, where power density and thermal performance ...
Indium Corporation
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Revolutionizing IC Packaging with High-Density RDL Technology
Amkor's S-SWIFT packaging technology addresses advanced IC packaging challenges through an embedded trace RDL process, providing higher bandwidth die-to-die interconnects for AI, HPC, and data center applications with improved reliability.
Technical Paper
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Full automation bond testers
A Sigma eliminates human error and comes with game-changing automation capabilities, robotic handlers, and smart vision cameras for operator-free bond testing and analysis. Learn more.
xyztec
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ASML goes beyond EUV and focuses on packaging
ASML is pivoting beyond transistor miniaturization as physical limits stall Moore's Law, investing heavily in advanced packaging and 3D chip stacking. With its Twinscan XT:260, the company targets AI-driven demand and positions itself across the entire semiconductor value chain.
Innovation Origins+
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Follow The AI Leader
The AI race in electronic design echoes IBM's once-safe dominance, but no clear leader has emerged. Tech giants build powerful in-house tools, EDA firms guard expertise & startups chase disruption, leaving a fragmented, unpredictable landscape as companies seek trusted AI partners.
Semiconductor Engineering
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3 Ways to Increase Plasma Uniformity
Process temperature is the most important parameter in the plasma process. Process temperature has primary control over etch rate and has a secondary effect on etch uniformity. Read more.
Plasma Etch
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MIPS, GlobalFoundries Bet on Physical AI
MIPS speeds its comeback by acquiring Synopsys's ARC IP and going all-in on RISC-V to target physical AI and automotive markets. With 200 million deployed SoCs and a Mobileye EyeQ7 win, it advances customizable, real-time, safety-certified chips for software-defined vehicles.
EE Times
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2026 IEEE ECTC – May 26-29 in Orlando
The Electronic Components & Technology Conference delivers the best in packaging, components & microelectronic technologies, held at the JW Marriott & The Ritz-Carlton Grande Lakes Resort, Orlando, FL.
ECTC
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AP Memory optimistic on demand
AP Memory Technology expects robust AI and HPC demand to lift revenue this year as clients pivot from scarce standard DRAM to customized memory. Growing silicon interposer and capacitor sales, along with new VHM chips, should fuel sustained growth despite last year's profit dip.
Taipei Times
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Temporary Bonding Materials
Boost throughput and quality with Brewer Science's BrewerBOND® VersaLayer temporary bonding system for high-temperature (400˚C) and high-stress applications.
Brewer Science
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Inside IISc Bangalore's CeNSE Lab: From Wafer to Finished Device
The Centre for Nano Science and Engineering at the Indian Institute of Science drives end-to-end semiconductor prototyping, from wafer fabrication to packaging and testing, helping startups and industry bridge research and early manufacturing to boost India's chip ecosystem.
EE Times
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New Challenges In Signoff
As multi-die architectures and advanced nodes heighten chip complexity, signoff grows tougher under tight deadlines. Marc Heyberger of Cadence Design Systems details full-chip timing, flat vs. hierarchical analysis, 3D-IC advances, and AI's rising role in design.
Semiconductor Engineering
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Research Bits: Mar. 3
Researchers boost chip defect detection with electron ptychography, a multimodal SQUID microscope, and combined microscopy. The tools expose atomic-scale flaws, interface roughness, and hidden stacking faults, speeding root-cause analysis and improving device reliability.
Semiconductor Engineering
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| Today's Sponsor |
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| Sponsor |
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Interested in a demonstration?
We want to prove to you that surface preparation with Surfx argon plasmas results in a superior bond. Submit a request and our staff will respond within the next business day.
Surfx Technologies
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Test Your Knowledge
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With reference to electronic components, what does the acronym SOIC stand for?
See answer below.
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Quote of the Day
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"Computers are useless. They can only give you answers." Pablo Picasso, 1967
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AIT ORMET® TLPS for Proven Reliability
AIT ORMET® TLPS is proven for outstanding reliability for High and Ultra High-Density Interconnection and high temperature build-up Layer Interconnection beyond 175°C
Ormet® TLPS
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| Cartoon of the Day
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"Are you part of the problem, part of the solution, part of the problem with the solution or part of the solution to the problem with the solution?"
Copyright © Randy Glasbergen
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Contamination Control
Balazs provides technical expertise in identifying and controlling Airborne Molecular Contamination (AMC) and Surface Molecular Contamination (SMC) for improving process and product yields.
Balazs Nanoanalysis
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Test Your Knowledge Answer
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With reference to electronic components, what does the acronym SOIC stand for? Answer: Small-Outline Integrated Circuit which is a surface-mounted integrated circuit (IC) package which occupies an area about 30 to 50% less than an equivalent dual in-line package (DIP), with a typical thickness that is 70% less.
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