May 1, 2026

Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes Device scaling slows while demand for leading-edge nodes surges, straining capacity dominated by TSMC and major chipmakers. Rising costs & limited access push the industry toward chiplets & advanced packaging, reshaping design choices, innovation paths & competition for smaller firms. Semiconductor Engineering

Sponsor Hermetic Microelectronic Package Seam Seal Technical paper on technology that delivers a pristine internal atmosphere for hi-rel microelectronic components. Process automation, including AI, and standard tooling utilized in die and wire bonding is standard. MicroCircuit Laboratories, LLC

Researchers Reportedly Develop Ultrafast Laser Wiring for Glass Substrates, Targeting CPO Bottleneck Chonnam National University researchers developed ULCVD, using femtosecond lasers to inscribe maskless carbon circuits on both sides of glass substrates. The advance enables flexible 3D interconnects, easing CPO bottlenecks and accelerating next-gen AI packaging. TrendForce

Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems This white paper explains why die-on-tab is critical for GaN and GaAs RF power devices, improving heat dissipation, reliability, and system life. Download now. Technical Paper

Sponsor Advanced Packaging for Next-Generation Vehicle As cars move to a central computing architecture, splitting SoCs into chiplets becomes a logical solution to size and cost challenges. Read more. Amkor Technology, Inc.

Intel's stock more than doubles in April for best month in chipmaker's 55 years on Nasdaq Intel shares surged 114% in April as a turnaround gains momentum, driven by rising AI-related CPU demand, promising 18A chips, and foundry ambitions. Government support and new customers fuel optimism despite past losses and execution challenges. CNBC

Micross Components Appoints James J. Cannon as President and Chief Executive Officer Micross Components appoints Jim Cannon as President and CEO, succeeding Vincent Buffa, who stays as senior advisor and board member. Cannon brings 25+ years defense and industrial leadership experience to drive growth in microelectronics for critical markets. 3DInCites

Sponsor 1 of 10 Applications: Flip-Chip Flip chip bonding at an accuracy of 5 µm or better is simple with Swiss made Tresky die bonders, at temperatures of up to 400°C, both in manual and in semiautomatic mode. Dr. Tresky AG

Technical Papers Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications Eliminating Interfacial Delamination in High-Power Automotive Devices MORE TECHNICAL PAPERS

Sponsor IR Layer Release Technology for 3D Packaging and Logic Scaling Ultra-thin layer transfer from silicon carriers with nanometer precision using an IR laser and inorganic release layers revolutionizes 3D packaging & logic scaling. EV Group

Athos Scraps Multi-Vendor Roadmap, Plans Chiplet Tape-Out Athos Silicon, spun out of Mercedes-Benz, has overhauled its roadmap to center on a single in-house chiplet, abandoning a multi-vendor design. The shift cuts costs and boosts control while preserving safety via redundant diagnostic voting compute. EE Times

Google cloud growth tops Microsoft and Amazon as all three beat estimates on AI demand Google, Amazon AWS, and Microsoft Azure beat earnings estimates as AI-driven cloud demand surged. Google led with record 63% growth, while AWS rose 28% and Azure 40%. Massive AI investment drives $600B capex and rising neocloud competition. CNBC

Sponsor Full automation bond testers A Sigma eliminates human error and comes with game-changing automation capabilities, robotic handlers, and smart vision cameras for operator-free bond testing and analysis. Learn more. xyztec

Samsung, SK Hynix flag record supply squeeze in memory market as AI demand soars Samsung Electronics and SK Hynix warn of a severe global memory chip supply crunch as AI demand surges. Orders outstrip capacity, HBM4 is fully booked, customers pre-book 2027 supply, and both firms post record profits while expanding China fabs. South China Morning Post

Transforming DRC Closure At Advanced Nodes As SoCs reach 2nm and below, engineers face massive DRC violation volumes and shifting constraints. Teams replace slow, batch debugging with real-time, AI-driven, instance-complete analysis that exposes all errors early, prioritizes fixes, and accelerates coordinated closure. Semiconductor Engineering

Sponsor How LAPLACE® Laser Assisted Bonding Saves Energy LAPLACE® enables fast, localized laser bonding with minimal heat exposure—cutting energy use while ensuring precision for sensitive advanced packaging processes. Watch Demo. PacTech

Creating Agentic EDA Methodologies EDA AI evolves from single-tool optimization to full agentic flows, but lack of architectural tools, fragmented abstractions, and inconsistent data hinder progress. Industry players explore LLMs, shift-left prediction & open interfaces to connect specifications through RTL while managing risk. Semiconductor Engineering

From Standards To Systems: The Chiplet Era On Arm Arm pivots from monolithic SoCs to chiplet-based designs, leveraging AMBA, ACSA, and OCP FCSA standards. It drives coherent data movement and system-level orchestration across heterogeneous compute, with partners like Baya Systems boosting scalable AI performance. Semiconductor Engineering

Sponsor Ultrasonic Bonding in semiconductor industry - The fast and clean process Ultrasonic die bonding enhances semiconductor assembly with strong bonds, reduced thermal stress, and advancements in 3D packaging technology. Tresky

NoC Coherency Challenges Balloon With AI SoCs And Chiplets Chip designers are confronting data movement as the main bottleneck in AI SoCs, forcing earlier NoC planning. They balance coherent and non-coherent networks for CPUs and accelerators, increasingly relying on commercial NoC IP to manage growing system complexity. Semiconductor Engineering

Sponsor SQ7000+TM Multi-Function for 3D AOI, SPI & CMM The SQ7000+ with MRS® sensor technology delivers high-resolution, high-speed inspection and metrology, uniquely combining AOI, SPI, and CMM in one in-line system. Nordson Test & Inspection