Oct 2, 2026 The Hidden Challenges of Edge AI Design Edge AI is pushing chip designers beyond peak NPU performance toward flexible architectures that balance memory, latency, power and security. Hardware-software co-design, scalable memory and built-in security help systems adapt as AI workloads evolve. Semiconductor Engineering

Sponsor Automotive chips need materials that DO NOT fail We asked semiconductor specialists what defines the future of automotive packaging. Reliability, thermal management, and sustainability topped the list. Free Research Report. Henkel AG & Co.

AI-Defined Vehicles Push Compute, Memory, And Validation Limits Automakers are evolving software-defined vehicles into AI-defined systems that can interpret data and adapt in real time. New architectures must balance compute, memory, power, safety, security and longevity as AI workloads expand across vehicles. Semiconductor Engineering

Bond front velocity in lubrication-mediated bonding of flexible substrates Robust theoretical model explaining bondwave velocity in direct wafer/die bonding and explaining why it accelerates. First model with predictive power to show realistic and observed values. Technical Paper

Sponsor Automotive chips need materials that DO NOT fail We asked semiconductor specialists what defines the future of automotive packaging. Reliability, thermal management, and sustainability topped the list. Free Research Report. Henkel AG & Co.

Computer science has long understood how to keep AI under control AI agents aren’t "going rogue" when they hack systems; they pursue assigned goals within loose constraints. Recent attacks by OpenAI, Anthropic and Google highlight the need for tighter limits, authentication and human oversight to prevent harm. Asia Times

Qualcomm Doubles Down on Agentic AI at Snapdragon Summit 2026 Qualcomm unveiled two flagship Snapdragon 8 Elite Gen 6 smartphone SoCs at its annual summit, accelerating development while advancing personal agentic AI. Tirias Research analysts also examined updates to Qualcomm’s wearable, hearable and PC platforms. EE Times

Sponsor Enabling A Chiplet Supply Chain Chiplet-based architectures are gaining popularity for their smaller die sizes and better yields, but challenges in power management, security, and supply chain complexity remain. Download now. Amkor Technology, Inc.

Technical Papers ■ Why Metal TIM Warpage Simulations Fail—and How to Fix Them ■ Oxide Reduction for Reliable Power Electronics Manufacturing ■ Bond front velocity in lubrication-mediated bonding of flexible substrates ■ How AI Could Cut Semiconductor Package Design Cycles from Months to Days ■ 5X Faster Die Sorting Accelerates U.S. Semiconductor Manufacturing ■ A New Optical Ball Grid Array Package Development for Automotive Optical Sensor ■ Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications MORE TECHNICAL PAPERS

Sponsor Openair-Plasma for Semiconductor Manufacturing Openair-Plasma for semiconductor production is an alternative to vacuum plasma. Typical apps are wire bonding, die bonding & pre-molding. Download here. Plasmatreat GmbH

Micron Taiwan accelerating expansion Micron is accelerating Taiwan memory expansion as AI demand intensifies, investing NT$1.6 trillion to date. It is upgrading Taoyuan for next-generation DRAM, adding HBM packaging capacity in Taichung and expanding fabs in Miaoli to meet demand. Taipei Times

Turning Edge AI Data Into Real-Time Action Edge AI is moving intelligence from data centers into devices, enabling real-time decisions with lower latency, improved privacy and reduced cloud dependence. Sensors, processors, memory and secure networks must work together. Semiconductor Engineering

Sponsor How to Wire Pull? Learn how to perform an optimal pull test on wires or ribbons. This extensive guide also covers loop height measurement, vector pull, and SMD gull-wing leads pull. Download now. xyztec

Memory At The Edge: Non-Volatile Memory Challenges And Requirements For Humanoid Robots Humanoid robots demand specialized memory architectures as deployments scale. High-bandwidth DRAM and NAND support AI workloads, while F-RAM and safety-focused NOR Flash deliver endurance, resilience and deterministic control at the robot edge. Semiconductor Engineering

Mitigating Threats With Pre-Silicon Security Verification Semiconductor security now demands end-to-end protection against hardware Trojans, data leaks, side-channel attacks and fault injection. Pre-silicon verification using static, formal and simulation methods helps secure chips before deployment. Semiconductor Engineering

Sponsor No-Clean, Flip-Chip and Ball-Attach Flux Improve yields with NC-809, the industry leading, true no-clean, ultra-low residue, flip-chip and ball-attach flux suitable for many semiconductor applications. Indium Corporation

Crossing Chiplet Boundaries With PCIe Over UCIe PCIe 8.0 over UCIe 3.0 enables high-bandwidth chiplet connectivity, but adds complex integration risks. Siemens Avery PCIe and UCIe VIP helps engineers verify power, reset, recovery, ordering and error handling across die boundaries before silicon. Semiconductor Engineering

Huawei steps up Tau chip roll-out, with Mate XT 2 on track for 1 million sales Huawei is advancing home-grown chip technology with Tau Scaling Law-based processors for its Mate 90 series. The move strengthens its response to US export curbs, while the Mate XT 2 trifold targets 1 million sales globally and expands overseas. South China Morning Post

Sponsor What is Hybrid Alignment? Passive and active alignment in one Tresky DIE Bonder ➜ powering flexible, high-precision assembly for advanced packaging. Tresky

The Semiconductor Silicon Wafer Market is projected to reach $21.71 billion by 2030, growing at a CAGR of 8.9% The semiconductor silicon wafer market is projected to grow from $14.12 billion in 2025 to $21.71 billion by 2030 as AI, data centers, consumer electronics and advanced chip production boost demand globally for larger, ultra-pure wafers now. EIN Presswire

Sponsor Plasma Etch PE-Avenger The PE-Avenger is an ultra low-cost entry level plasma cleaning system allowing more labs to utilize plasma. It's a low frequency plasma cleaner designed for surface activation and organics removal. Plasma Etch

TSMC's 3-nm Ramp Looks Different in Historical Context TSMC's 3-nm process is nearing revenue leadership, reaching 30% of wafer revenue in Q2 2026. Historical comparisons show 7nm ramped faster, highlighting how inherited manufacturing learning, customer demand, capacity growth, and product mix shape each node's trajectory. EE Times