Oct 16, 2026 How Close Are We To Fully Autonomous Chip Design? Synopsys CEO Sassine Ghazi explains how AI is transforming chip design by integrating physics, materials, manufacturing processes, software, and AI models. He emphasizes co-designing and optimizing the entire technology stack to meet evolving workloads and engineering demands. Semiconductor Engineering

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GlobalFoundries gets US$21bn for plants in US-Japan deal GlobalFoundries plans two New York chip plants backed by up to US$21 billion in Japanese investment, while the US takes a 4% stake. The expansion aims to boost essential chip production, strengthen supply-chain security and meet surging demand. Taipei Times

Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications This paper explores how, with chips becoming smaller and mightier, automated x-ray metrology delivers game-changing quality and efficiency in wafer and panel level applications, while delving into industry trends. Technical Paper

Sponsor Die Attach Material Comparisons Packaging high-power GaN devices? This study compares CuW and CMC bases with H20E and AuSn, revealing 34.5°C cooler junctions with CMC/AuSn. Revolutionize GaN efficiency/reliability. StratEdge Corporation

Smartphone shipments crash 22% in worst quarter ever, research group says Global smartphone shipments plunged 22% to 255.3 million units in the third quarter as AI-driven memory costs surged. IDC said rising prices hurt Chinese brands, favored premium vendors Apple and Samsung, and threatened recovery until 2028. Taipei Times

TSMC eyes adding facilities in Texas TSMC is evaluating Texas wafer capacity with a customer developing the TeraFab project, while insisting on operational control. Driven by surging AI demand, the chipmaker plans US expansion, increased advanced-chip production, and expects strong revenue growth. Taipei Times

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Technical Papers ■ Selective Alkaline Wet Etching of Al and AlCu Using a Phosphoric and Nitric Acid Free Formulation ■ Hybrid & Fusion Bonding: from Heterogeneous Integration to 3D Front-End of Line Technologies ■ Why Metal TIM Warpage Simulations Fail—and How to Fix Them ■ Oxide Reduction for Reliable Power Electronics Manufacturing ■ Bond front velocity in lubrication-mediated bonding of flexible substrates ■ How AI Could Cut Semiconductor Package Design Cycles from Months to Days ■ 5X Faster Die Sorting Accelerates U.S. Semiconductor Manufacturing MORE TECHNICAL PAPERS

Sponsor From Heterogeneous Integration to 3D Front-End of Line Technologies This paper explores how hybrid and fusion wafer bonding have become foundational technologies in enabling both "More than Moore" heterogeneous integration and "More Moore" transistor scaling & recent advancements driving future architectures. EV Group

TSMC chip capacity is 'fierce' battleground for AI customers, amid record quarter TSMC faces mounting capacity constraints as surging AI demand overwhelms its advanced chipmaking facilities. The company is expanding globally, but years-long construction timelines push customers toward Samsung and Intel while intensifying competition for scarce wafer supply. CNBC

Small Volumes, Big Impact: Europe's Hidden Role in Advanced Chipmaking Fraunhofer ISIT builds specialized chips for IMS Nanofabrication's multibeam electron-beam systems, enabling advanced EUV photomask production. Its expertise in complex, low-volume manufacturing supports cutting-edge chipmaking at Intel and TSMC. EE Times

Sponsor Dicing Die-Attach Film (DDAF) or Dicing Die-Attach Tape (DDAT) AI Technology pioneered the use of flexible die-attach film and paste adhesives for larger chip and die bonding. We now have extended our adhesive line. See more AI Technology, Inc.

TSMC confirms talks with Elon Musk over Texas 'Terafab' but insists on operational control TSMC is discussing a potential role in Elon Musk's Terafab chip project in Texas but insists on retaining operational control. Surging AI demand drives TSMC's expansion plans as record profits and rising investments support increased semiconductor production. South China Morning Post

Building AI Infrastructure For Greater Choice And Flexibility AI infrastructure increasingly combines specialized memory, compute, connectivity and packaging to meet distinct training and inference needs. Standards such as UCIe enable flexible chiplet integration, helping designers balance performance, power, cost and efficiency. Semiconductor Engineering

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Why Open-Weight AI Matters Open-weight AI models offer chip designers greater flexibility, lower costs, and improved data privacy through local deployment. However, rapidly evolving workloads, hardware demands, and proprietary design data require adaptable platforms, specialized training & careful model routing. Semiconductor Engineering

Agentic AI Alters The CPU-GPU Balance Agentic AI shifts computing demands toward CPUs, which orchestrate models, make decisions, and execute actions. While GPUs power LLMs and reasoning models, agents coordinate multiple systems autonomously, potentially changing CPU-to-GPU ratios as adoption accelerates. Semiconductor Engineering

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Thermal Co-Simulation Testing of Co-Packaged Optics Ayar Labs and GUC used thermal co-simulation to validate co-packaged optics in AI packages exceeding 3 kW. Tests showed air cooling fails, while liquid-cooled cold plates keep all components within temperature specifications. Semiconductor Engineering

Sponsor Lab Bonder for Microelectronics & Photonics Tresky's Lab Bonder for advanced packaging provides accuracy of ±0.7 μm for reproducible submicron bonding processes in R&D and emerging applications. Tresky

New technique controls exactly where 2D semiconductor crystals grow KAIST researchers developed a technique to precisely control where 2D semiconductor crystals grow, achieving single-crystal formation in over 99% of 400 patterns. The breakthrough could enable faster, more energy-efficient stacked AI chips. Nanowerk