June 2, 2026

The Sub-2nm Paradox At 2nm and below, chip scaling strains physics and manufacturing as RC delays, SRAM lag, and process variability reduce yields and raise costs. The industry responds with chiplets, advanced packaging, new transistor architectures, and material innovations driven by AI demand. Semiconductor Engineering

Sponsor The Next Step in Surface Prep! All-new Ontos Clean Atmospheric Plasma System. Create pristine, atomically-controlled, activated surfaces without a vacuum chamber. Ontos Equipment Systems

TSMC Defends Transistor Scaling Amid Huawei's 'Her's Law' Proposal At TSMC's European Symposium, Kevin Zhang challenged Huawei's "Tao scaling" approach, arguing EUV-driven transistor scaling remains vital. He cited roughly 30% energy gains while endorsing 3D integration, CFETs, and advanced stacking technologies as key complements. EE Times

The Evolution of Inspection and Metrology in the AI Era AI's rise drives demand for advanced processors, shifting the industry to chiplet architectures with high-bandwidth memory. This transformation introduces new challenges in semiconductor manufacturing, especially in inspection and metrology. Technical Paper

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Intel Advances Glass Substrate Push with 3DGS, US$3.3 Billion India Plant Set for Five-to-Six-Year Buildout Intel advances its glass substrate strategy with 3DGS, investing $3.3B to build a semiconductor packaging plant in Odisha, India, targeting 70,000 substrates annually and scaling AI chip packaging as global rivals race to commercialize glass tech. TrendForce

US takes steps to close loophole that let firms export Nvidia AI chips to China The U.S. Commerce Department is closing a loophole that let advanced AI chips, including Nvidia Blackwell processors, reach Chinese firms through overseas subsidiaries. New licensing rules will apply globally to China-based companies, tightening export controls. Taipei Times

Sponsor What do 81.3 % of automotive chip specialists agree on? That high-performance packaging materials are essential for reliability. The Research Report from Henkel Adhesive Technologies puts a number on what the industry feels. Henkel AG & Co.

Technical Papers Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications MORE TECHNICAL PAPERS

Sponsor New Quadra Pro Manual X-Ray System Sets a new standard for high-resolution 3D/2D manual inspection with exceptional image clarity and reduced noise levels Learn more. Nordson TEST & INSPECTION

AI agents to replace smartphones as center of digital life: Qualcomm CEO Qualcomm CEO Cristiano Amon said AI agents will replace smartphones as the center of digital life, transforming devices into connected endpoints, enabling continuous assistance across platforms & triggering a major computing upgrade cycle, with 2026 marking the 'year of agents.' Taipei Times

Nvidia launches AI chip for Windows-based laptops Nvidia unveiled RTX Spark (N1X) chip for Windows laptops, enabling agentic AI on edge devices. Built with MediaTek on TSMC 3nm, it powers new AI PCs with Microsoft, signaling a reinvention of personal computing and expanding AI-driven digital labor. Taipei Times

Sponsor Improve BGA Rework Reliability with Proven Reballing Methods BGA reballing requires precision, process control, and an understanding of failure risks. This guide covers techniques, common defects, and best practices. Circuit Technology Center

Early Memory Contention Checks Reduce IC Design Risks Growing SoC, AI accelerator, and graphics complexity exposes memory contention and reliability risks that cause costly failures. Engineers now adopt shift-left schematic-level analysis to detect issues early, improve collaboration, reduce redesigns, and build more reliable silicon systems. EE Times

India targets $150 billion semiconductor value chain through packaging, design and manufacturing push India launches a 10-year semiconductor roadmap aiming to build a $120–150 billion value chain, expand chip design, advanced packaging and compound semiconductors & strengthen talent, partnerships and innovation to reduce import dependence & boost AI-driven digital infrastructure. CRN India

Sponsor Seam Seal Data Collection Robotic Cover Sealer (RCS) is a fully digital, automated seam seal process using AI. Complete data is provided on each package and lid. MicroCircuit Laboratories LLC

Nikon Leveraging ArF Scanner Price to Challenge ASML Nikon plans to cut lithography equipment prices by manufacturing more parts in-house while negotiating ArF tool deals with chipmakers. It will launch a new immersion platform by 2028, aiming for ASML compatibility and positioning itself as a lower-cost second source. EE Times

AI revolution is '50x bigger' than the dot-com boom: SoftBank's Masayoshi Son to CNBC SoftBank CEO Masayoshi Son called AI a revolution 50 times larger than the dot-com boom, arguing any market correction would create opportunity. Backing that view, SoftBank pledged €75 billion to expand AI infrastructure in France and deepen its global AI push. CNBC

Sponsor IR Layer Release Technology for 3D Packaging and Logic Scaling Ultra-thin layer transfer from silicon carriers with nanometer precision using an IR laser and inorganic release layers revolutionizes 3D packaging & logic scaling. EV Group

NVIDIA and TSMC Bring AI Into Fabs to Advance Semiconductor Design and Manufacturing NVIDIA announced that TSMC is deploying its accelerated computing and AI tools across semiconductor design and manufacturing to improve speed, yield & efficiency. The collaboration enhances lithography, inspection & simulation, including virtual fab modeling with Omniverse. Global Newswire

Sponsor 1 of 10 Applications: Flip-Chip Flip chip bonding at an accuracy of 5 µm or better is simple with Swiss made Tresky die bonders, at temperatures of up to 400°C, both in manual and in semiautomatic mode. Dr. Tresky AG